The present invention relates to a novel semiconductor device having a capacitance device.
One type of non-volatile memory cell is a metal-oxide-nitride-oxide substrate (MONOS), wherein a gate insulating layer between the channel and the gate is formed of a multi-layer stack of a silicon oxide layer and a silicon nitride layer, and charge is trapped in the silicon nitride layer.
A device shown in FIG. 17 is known as an example of this MONOS type of non-volatile memory cell (disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In this MONOS memory cell 102, a word gate 14 is formed on a semiconductor substrate 10 with a first gate insulating layer 12 therebetween. A first control gate 20 and a second control gate 30 are formed on either side of the word gate 14, in the shape of side walls. There is a second gate insulating layer 22 between a base portion of the first control gate 20 and the semiconductor substrate 10, and an insulating layer 24 between a side surface of the first control gate 20 and the word gate 14. In a similar manner, there is a second gate insulating layer 32 between a base portion of the second control gate 30 and the semiconductor substrate 10, and an insulating layer 34 between a side surface of the second control gate 30 and the word gate 14. An impurity layer 16 or 18, which is to form a source region or drain region, is formed in the semiconductor substrate 10 between the opposing control gates 20 and 30 of neighboring memory cells.
In this manner, each memory cell 102 has two MONOS memory elements on the side surfaces of the word gate 14. These two MONOS memory elements can be controlled independently, and thus the memory cell 102 can store two bits of information.
The operation of these MONOS memory elements is as described below. Each control gate of the memory cell 102 can be selected independently for writing and reading by biasing the other control gate by an overwrite voltage.
The description now concerns writing (programming), using a case in which electrons are implanted into a second gate insulating layer (ONO film) 32 on the left side of CG[i+1], as shown in FIG. 17. In this case, the bit line (impurity layer) 18 (D[i+1]) is biased by a drain voltage of 4 to 5 V. Since the control gate 30 (CG[i+1]) causes implantation of hot electrons into the second gate insulating layer 32 on the left side of the control gate 30 (CG[i+1]), it is biased to 5 to 7 V. Since the write current in the word line connected to the word gates 14 (Gw[i] and Gw[i+1]) is limited to a predetermined value (up to 10 μA), the word line is biased to a high voltage that is less than the threshold voltage of the word gate. The control gate 20 (CG[i]) is biased by an overwrite voltage. This overwrite voltage makes it possible to make a channel below the control gate 20 (CG[i]) conductive, regardless of the storage state. The bit line 16 (D[i]) on the left side is biased to the ground potential. The control gates and impurity layers of the other, non-selected memory cells are set to the ground potential.
For erasure, the accumulated charge (electrons) are erased by the implantation of hot holes. The hot holes can be generated by B—B tunneling in the surface of the bit impurity layer 18. During this time, the voltage Vcg of the control gates is negative (−5 to −6 V) so the voltage of the bit impurity layer is biased to 5 to 6 V.
This document discloses how the above described MONOS type of memory cell has two programming sites within one memory cell that can be controlled independently, to enable a bit density of 3F2.
As memory cells become smaller, there is a requirement for a reduction in size of capacitance devices comprised within an analog IC of the peripheral circuit section of such a memory cell.